The present invention relates to a semiconductor memory device and, more particularly, to a semiconductor memory device that reduces power consumption during a refresh operation.
In a DRAM device, a refresh operation is conducted to preserve data that is stored within the memory cells of the DRAM device. The refresh operation involves a sequence of procedures by which data stored in the memory cells is read out, amplified, and restored in the memory cells. As is known, DRAM memory cells include capacitors and, thus, the absence of a refresh operation allows the leakage current of these capacitors to cause a loss of data stored in the DRAM memory cells.
FIG. 1A is a schematic diagram of a conventional refresh block. As shown in FIG. 1A, the conventional refresh block includes a controller 110 for generating a counter active signal CNT_AC and a row active signal R_AC in response to an auto-refresh signal A_REF that is activated during an auto-refresh operation and a self-refresh signal S_REF that is activated during a self-refresh operation. The conventional refresh block also includes a refresh counter 130, which responds to the counter active signal CNT_AC and which generates a row address signal R_AD and a bank address signal B_AD[0:3] that are used to select an address of the memory cell to be refreshed. Additionally, the refresh block includes a bank selector 150, which responds to the row active signal R_AC and the bank address signal B_AD[0:3] to generate a bank enable signal B_EN[0:3] that is used to control access to a bank of memory cells, including the memory cell to be refreshed.
FIG. 1B is a detailed block diagram of the refresh counter 130 shown in FIG. 1A. As shown in FIG. 1B, to generate the row address signal R_AD and the bank address signal B_AD[0:3] in response to the counter active signal CNT_AC from the controller 110, the refresh counter 130 includes a plurality of unit counters 131-133 that generate an internal address signal I_AD[1:N]. The number of unit counters typically corresponds to the number of address bits outputted by each unit counter.
The operation of the conventional refresh block will now be described with reference to FIGS. 2A and 2B. FIG. 2A is a timing diagram of a prior art refresh operation and FIG. 2B is a timing diagram in a 64M SDRAM having 4 k cycles.
In the DRAM, the refresh operation includes an auto-refresh operation and a self-refresh operation. If such a refresh operation is activated, an overall memory cell is accessed to read out data stored in the memory cell that is to be restored in the memory cell. To access the memory cell, the refresh counter 130 generates the internal address signal, which is synchronized with the enabling of the auto-refresh operation and the self-refresh operation, to design a memory cell between banks, performing the refresh operation. Specifically, if the auto-refresh signal A_REF or the self-refresh signal S_REF is activated, the controller 110 enables the counter active signal CNT_AC and the row active signal R_AC.
In response to the counter active signal CNT_AC, the refresh counter 130 is enabled to activate the plurality of unit counters 131-133, which output the two highest bits of the internal address signal I_AD[1:N] to be used as the bank address signal B_AD[0:3]. The remaining bits are not used as the row address signal R_AD, wherein the row address signal R_AD enables a word line to be refreshed.
As shown in FIG. 2A, if the auto-refresh operation or the self-refresh operation is enabled, the counter active signal CNT_AC is enabled to allow the internal counter to be enabled, thereby permitting all memory cells in all banks to be refreshed. However, the number of memory cells to be refreshed during one cycle is increased with the level of integration in memory devices and the level of power consumption rises in proportion to the increase in the number, which results in a considerable amount of current consumption during the refresh operation.
The 64M-DRAM has a refresh cycle of 4 Kcycles/64 ms, meaning that all 64M memory cells should be refreshed through 4 k refresh operations at 64 ms. In other words, each memory cell should be refreshed every 64 ms, which is commonly referred to as a xe2x80x9ccell retention time.xe2x80x9d To accomplish this, 16 k cells should be refreshed every refresh cycle. This corresponds to 4 k cells per each bank in a four-bank system. Accordingly, the prior art refresh block suffers from a drawback that the power consumption increases with the number of cells to be refreshed in such a manner that in 128M DRAM, 32 k cells per one cycle are refreshed, and in 256M DRAM, 64 k cells per one cycle are refreshed and the like.
A semiconductor memory device generates an address during a refresh operation that is used to address a memory cell. The memory device includes a controller for generating a refresh signal in response to an auto-refresh signal and a self-refresh signal. The memory device may further include a bank counter that generates a bank selection signal and a bank count signal, which are used in selecting a bank in response to the refresh signal. Still further, the memory device may include a bank selector that generates a first and a second bank enable signal, which are used in selectively enabling each bank in response to the bank selection signal and the bank count signal, a refresh counter controller that generates a counter active signal in response to the bank selection signal and the refresh signal, and a refresh counter that generates a row address signal, which is used in addressing for access to the memory cell in response to the counter active signal.